1. Field of the Invention
The present invention relates to a method for driving a plasma display panel (PDP).
The PDP is a self-luminous type display device with a characteristic good discernment (i.e., high resolution) and with a thin and large display screen. The PDP is attracting attention as a display device with which CRTs will be replaced in the near future. In particular, a surface discharge AC type PDP is highly expected to be a display device compatible with high-quality digital broadcasting, because it can be designed to have a large display screen. The surface discharge AC type PDP will be required to provide a higher quality than a CRT.
A high-quality display may be construed as a high-definition display, a display with a large number of gray-scale levels, a high-luminance display, or a high-contrast display. A high-definition display is accomplished by setting the pitch between pixels to a small value. A display with a large number of gray-scale levels is accomplished by increasing the number of sub-fields within a frame. Moreover, a high-luminance display is accomplished by increasing the amount of visible light permitted by certain power or increasing the number of times of sustain discharge. Furthermore, a high-contrast display is accomplished by minimizing the reflectance of extraneous light from the surface of a display panel or minimizing an amount of glow that occurs during black display which does not contribute to the display.
2. Description of the Related Art
The structure of a conventional plasma display panel and a conventional method for driving a plasma display panel will be described with reference to FIG. 1 to FIG. 4 to be described later in “BRIEF DESCRIPTION OF THE DRAWINGS”. This is intended to facilitate an understanding of problems underlying the conventional method for driving a plasma display panel.
FIG. 1 schematically shows the structure of a surface discharge type PDP in which a method, filed for a patent by the present applicant, is implemented. According to the method, lines defined by all sustain discharge electrodes are involved in display. The structure of the PDP has been disclosed in, for example, the specification and drawings of Japanese Unexamined Patent Publication No. 9-160525 published on Jun. 20, 1997.
A PDP 1 consists of sustain discharge electrodes X1 to X3 (hereinafter abbreviated to X1 to X3 electrodes) and Y1 to Y3 (hereinafter abbreviated to Y1 to Y3 electrodes), addressing electrodes A1 to A4, and barriers 2. The above sustain discharge electrodes are juxtaposed in parallel with each other on one substrate. The addressing electrodes are formed to cross the sustain discharge electrodes on the other substrate. The barriers 2 are arranged in parallel with the addressing electrodes, thus separating discharge spaces from each other. A discharge cell is formed in areas defined by the mutually adjoining sustain discharge electrodes and the addressing electrodes crossing the sustain discharge electrodes. Phosphors used to produce visible light are placed in the discharge cells. A gas for bringing about discharge is sealed in a space between the substrates. In this drawing, for brevity's sake, the sustain discharge electrodes are arranged parallel to each other in threes, and the addressing electrodes number four.
In the PDP having the foregoing structure, sustain discharge is induced in lines defined by each sustain discharge electrode and sustain discharge electrodes on both sides thereof. Interspaces or lines (L1 to L5) defined by all the electrodes therefore can work as display lines. For example, the X1 electrode and Y1 electrode define a display line L1, and the Y1 electrode and X2 electrode define a display line L2.
FIG. 2 shows a sectional view of the PDP shown in FIG. 1 along an addressing electrode. There are shown a front substrate 3, a back substrate 4, and discharges D1 to D3 induced in lines defined by electrodes. In practice, a voltage is applied to the Y1 electrode and X1 electrode. This induces the discharge D1. When a voltage is applied to the Y1 electrode and X2 electrode, the discharge D2 is induced. The discharge D3 is induced by applying a voltage to the X2 electrode and Y2 electrode. Thus, one electrode is utilized for providing display lines on both sides thereof. Consequently, a high-definition display can be achieved owing to a decreased number of electrodes. Besides, the number of drive circuits for driving the electrodes can be reduced accordingly.
FIG. 3 shows a frame configuration employed in the PDP shown in FIG. 1. One frame is composed of two fields of a first field and second field. During the first field, odd-numbered lines (L1, L3 and L5) are used as display lines to be involved in the display. During the second field, even-numbered lines (L2, L4) are used as display lines to be involved in the display. Thus, a picture for one screen is displayed during one frame. Each field consists of a plurality of sub-fields for which luminance levels are set in a predetermined ratio. Cells constituting display lines are selectively allowed to glow according to display data during the sub-fields. Thus, gray-scale levels construed as differences in luminance among pixels are expressed. Each sub-field consists of a reset period, an addressing period, and a sustain discharge period. During the reset period, the states of cells that are mutually different depending on the display situation over an immediately preceding sub-field are uniformed. During the addressing period, new display data is written. During the sustain discharge period, sustain discharge is induced in the cells constituting display lines so that the cells are allowed to glow according to display data.
FIG. 4 is a waveform diagram concerning a conventional driving method implemented in the PDP shown in FIG. 1. FIG. 4 is concerned with any sub-field within the first field.
During the reset period, a reset pulse of a voltage Vw exceeding a discharge start voltage is applied to all the X electrodes. Discharge is initiated in the lines defined by the X electrodes and adjoining Y electrodes. As a result, first discharge (reset discharge) is induced in all the lines (L1 to L5). Wall charges including positively-charged ions and electrons are produced in the discharge cells. Thereafter, the reset pulse is removed and the electrodes are retained at the same potential. Second discharge (self-erase discharge) is then induced due to the potential difference generated by the wall charges produced on the electrodes. At this time, since the electrodes are retained at the same potential, positively-charged ions and electrons stemming from discharge are recombined with each other within the discharge spaces. Consequently, the wall charges disappear. The magnitude of wall charges in all the display cells can be uniformed with the discharge (the distribution of wall charges is uniformed).
During the next addressing period, a scanning pulse of a voltage−Vy is applied successively to the electrodes starting with the Y1 electrode. An addressing pulse of a voltage Va is applied to the addressing electrodes according to display data. Consequently, addressing discharge is initiated. At this time, a pulse of a voltage Vx is applied to the X1 electrode to be paired with the Y1 electrode to participate in the display within the first field. Discharge having been induced in the spaces defined by the addressing electrodes and the Y1 electrode shifts to the line between the X1 electrode and Y1 electrode. Consequently, wall charges needed to initiate sustain discharge are produced near the X1 electrode and Y1 electrode. The potential at the X2 electrode to be paired with the Y1 electrode to define a line not involved in the display is retained at 0 V. It is therefore prevented that discharge is induced in the line defined by the X2 electrode. Likewise, addressing discharge is induced successively in the odd-numbered Y electrodes.
After the addressing discharge induced in the odd-numbered Y electrodes is completed, a scanning pulse is applied to the Y2 electrode. At this time, a pulse of a voltage Vx is applied to the X2 electrode to be paired with the Y2 electrode to thus participate in the display. The X3 electrode that is not shown is, like the X1 electrode, retained at 0 V. Likewise, addressing discharge is induced successively in the even-numbered Y electrodes. Consequently, addressing discharge is induced in the odd lines in the whole screen.
Thereafter, during the sustain discharge period, a sustain pulse of a voltage Vs is applied alternately to the X electrodes and Y electrodes. At this time, the phase of the sustain pulse is set so that a potential difference between paired electrodes defining a line not involved in display will be 0 V. It is thus prevented that discharge is induced in non-display lines. For example, sustain pulses that are mutually out of phase are applied to the pair of the X1 and Y1 electrodes participating in the display over the first field. In contrast, sustain pulses that are mutually in phase are applied to the pair of the Y1 and X2 electrodes defining a non-display line. Display is thus achieved over the first sub-field.
In FIG. 4, the voltage Vs is a voltage needed to induce sustain discharge and is usually set to about 170 V. Moreover, the voltage Vw is a voltage exceeding the discharge start voltage and set to about 350 V. The voltage−Vy of the scanning pulse is set to about−150 V, and the voltage Va of the addressing pulse is set to about 60 V. The sum of the absolute values of the voltages Va and Vy will be equal to or larger than the discharge start voltage with which discharge is initiated in the spaces defined by the addressing electrodes and each Y electrode. Moreover, the voltage Vx is set to about 50 V or a value causing discharge induced in the line defined by the addressing electrodes and each Y electrode to shift to the line defined by an X electrode. The value must enable production of sufficient wall charges.
However, according to the foregoing conventional driving method, reset discharge is adopted. The pulse of the voltage Vw exceeding the discharge start voltage, with which discharge is initiated in discharge cells, is applied to the X electrodes. This results in intense discharge. Light emission stemming from the discharge is background light emission having no relation to the display of a picture. This leads to a deterioration in the contrast of the picture.
Moreover, in the foregoing driving method using the lines defined by all the sustain discharge electrodes as display lines, there is a possibility that reset discharge may not be induced stably in all the discharge cells. In other words, the reset pulse is applied to all the X electrodes in order to induce discharge in all display lines. A discharge start time at which discharge is initiated in each discharge cell differs from discharge cell to discharge cell. There is a possibility that discharge may not be induced in some cells.
Referring back to FIG. 2, the X2 electrode will be discussed. If discharge D2 is induced first in the line between the X2 electrode and Y1 electrode, charges stemming from the discharge start to be accumulated near the electrodes. The wall charges generate a bias voltage of the opposite polarity to the voltage Vw and an effective voltage in the discharge space decreases. More particularly, wall charges are produced on the X2 electrode due to electrons. The wall charges cause the effective voltage of the voltage Vw applied to the X2 electrode in the discharge space to drop. The drop in the effective voltage may precede the initiation of discharge in the line between the X2 electrode and Y2 electrode. In this case, although discharge is not induced in the line between the x2 electrode and Y2 electrode, the reset period may come to an end. If reset discharge is not induced in some discharge cells, the states of the cells are not uniformed. Consequently, addressing discharge cannot be induced stably in the discharge cells. This leads to erroneous display.
Even if reset discharge is induced in all the cells, subsequent self-erase discharge may not be induced stably. The self-erase discharge is induced due to the potential difference generated by the wall charges stemming from reset discharge. The self-erase discharge may often be smaller in scale that the reset discharge. Depending on a difference in characteristics from discharge cell to discharge cell, the self-erase discharge may not be induced but wall charges stemming from the reset discharge may remain intact. Otherwise, when the reset discharge is completed, sufficient wall charges may not be produced and the self-erase discharge may not be induced. Consequently, subsequent addressing discharge is not induced normally in discharge cells that have not undergone erase discharge. This causes erroneous display.
As a method for solving the above problems, it is conceivable to raise the voltage of the reset pulse to induce discharge reliably in all cells. However, a further rise in discharge voltage will intensify the aforesaid background light emission and deteriorate the contrast of the picture.
If the reset period shifts to the addressing period with wall charges remaining intact in discharge cells because of the aforesaid cause, another problem arises. During the addressing period, as mentioned above, the voltage Vx is applied to X electrodes defining display lines. The other X electrodes defining non-display lines are held at 0 V, thus preventing the occurrence of addressing discharge. However, if unnecessary wall charges remain intact, discharge may be induced in the non-display lines.
For example, referring to FIG. 2, the scanning pulse of the voltage−Vy is applied to the Y1 electrode. The addressing pulse of the voltage Va is applied to the addressing electrodes, whereby addressing discharge is induced. At this time, since the voltage Vx is applied to the X1 electrode, the addressing discharge is succeeded by discharge to be induced in the line between the Y1 electrode and X1 electrode. Namely, discharge D1 is induced. At this time, the X2 electrode adjoining the Y1 electrode is held at 0 V. Induction of discharge D2 can be avoided in principle. However, the discharge D2 may be induced due to deflection of residual charges deriving from uncertainty of reset discharge. Consequently, wall charges of negative polarity are accumulated on the X2 electrode. Subsequent addressing discharge D3 is affected by the wall charges. Incidentally, there is a possibility that erroneous discharge caused by electrodes not participating in the display may also be caused by a difference in discharge start voltage from discharge cell to discharge cell.
Moreover, sustain discharge induced during each sub-field may spread depending on the sustain discharge voltage Vs or cell structure. Referring to FIG. 6, when sustain discharge is induced in the lines between the X1 and Y1 electrodes and between the X2 and Y2 electrodes, wall charges are accumulated over the electrodes Y1 and X2 to some extent. These wall charges are erased during the reset period within each sub-field. Wall charges formed on the addressing electrodes may not be erased but remain intact. The wall charges do not affect subsequent discharge to be induced within a field within which the lines between the X1 and Y1 electrodes and the X2 and Y2 electrodes are involved in display. The wall charges destabilize addressing discharge to be induced within the next field within which the line between the Y1 and X2 electrodes is involved in the display.